Hierarchical Design Methodologies of VLSI Integrated Circuits using a set of free tools call Alliance

In this Paper we present the hierarchical designs methodologies for integrated Circuits (IC) for a Very Large Scale Integration (VLSI) using free CAD tools Alliance. Alliance allow us to capture our digital designs through a hardware description language VHDL. Unlike the small digital systems which complete description can be included in a single VHDL file, the ICs designs for a medium and large size (e.g. VLSI) can only done by using a hierarchical design methodologie. In the hierarchical methodologies, the complete system is divided into different modules. After that a behavioral description VHDL is made for each of the modules of lower hierarchical level along with partial synthesis. With the partial synthesis we obtain some performance metrics for each module (initially describe in VHDL-behavioral) and verify the Functionality is one required. The modules of higher hierarchical levels are described in structural VHDL instantiating modules previously described. In this paper we describe two variants of hierarchical design, which have been used successfully at the University of Guadalajara, Campus CUCEI, in designing 2-IC (integrated circuits) sent to The MOSIS Service for manufacturing.